VLSI - Full time Program
ADVANCED DIPLOMA IN ASIC DESIGN -- FULL CUSTOM
- No of students per batch : Upto 15
- Course Duration: 6 months (1000 hrs)
- Placement statistics: 90% Placement
March 2025
ADVANCED DIPLOMA IN ASIC DESIGN -- RTL VERIFICATION
- No of students per batch : Upto 15
- Course Duration: 4 months (640 hrs)
- Placement statistics: 85% Placement
March 2025
ADVANCED DIPLOMA IN ASIC DESIGN -- PHYSICAL DESIGN
- No of students per batch : Upto 15
- Course Duration: 6 months (1000 hrs)
- Placement statistics: 90% Placement
March 2025
VLSI - Part time Program
Linux for VLSI Engineers
- No of students per batch : Upto 12
- Course Duration: 4 days (Saturdays / Sundays
- Placement statistics: Enquire at institute for details
RTL Design using Verilog (Bridge Course for non VLSI Engineers).
- No of students per batch : Upto 16
- Course Duration: 12 days (12 Saturdays)
- Placement statistics: Enquire at institute for details
RTL Verification using System Verilog.
- No of students per batch : Upto 12
- Course Duration: 12 days (12 Saturdays)
- Placement statistics: Enquire at institute for details
IC Layout design and optimization techniques (Full Custom Layout Design).
- No of students per batch : Upto 16
- Course Duration: 16 days (16 Saturdays)
- Placement statistics: Enquire at institute for details
Static Timing Analysis of VLSI Designs.
- No of students per batch : Upto 16
- Course Duration: 12 days (12 Saturdays)
- Placement statistics: Enquire at institute for details
ASIC Physical Design (PD) for Deep Submicron process nodes.
- No of students per batch : Upto 15
- Course Duration: 3 Weeks
- Placement statistics: Enquire at institute for details